Circuit underutilization

Not to be confused with Circuit minimization for Boolean functions, which is logical optimization rather than physical.

Circuit underutilization also programmable circuit underutilization, gate underutilization, logic block underutilization refers to a physical incomplete utility of semiconductor grade silicon on a standarized mass-produced circuit programmable chip, such as a gate array type ASIC, an FPGA, or CPLD.

Gate array

In the example of a gate array, which may come in sizes of 5,000 or 10,000 gates, a design which utilizes even 5,001 gates would be required to use a 10,000 gate chip. This inefficiency results in underutilization of the silicon.[1]

FPGA

Due to the design components of FPGA into logic blocks, simple designs that underutilize a single block suffer from gate underutilization, as do designs that overflow onto multiple blocks, such as designs that use wide gates.[2] Additionally, the very generic architecture of FPGAs lends to high inefficiency; multiplexers occupy silicon real estate for programmable selection, and an abundance of flip-flops to reduce setup and hold times, even if the design does not require them,[1] resulting in 40 times less density than of standard cell ASICs.

References

  1. 1 2 http://chipdesignmag.com/display.php?articleId=386
  2. ↑ http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.52.3689&rep=rep1&type=pdf Designing for High Speed-Performance in CPLDs and FPGAsZeljko Zilic, Guy Lemieux, Kelvin Loveless, Stephen Brown, and Zvonko Vranesic Department of Electrical and Computer Engineering, University of Toronto, Canada


This article is issued from Wikipedia - version of the 7/25/2016. The text is available under the Creative Commons Attribution/Share Alike but additional terms may apply for the media files.