Zero instruction set computer

In computer science, Zero Instruction Set Computer (ZISC) refers to a computer architecture based on pure pattern matching and absence of (micro-)instructions in the classical sense.

The ZISC acronym alludes to the previously developed RISC (Reduced Instruction Set Computer) technology.

History

ZISC is a technology based on ideas from artificial neural networks and massively hardwired parallel processing. This concept was invented by Guy Paillet.^[1]

Zero instruction set computers should not be confused with analogue computers. Analogue computers do not have the ability to carry out instructions.

Design features

The ZISC architecture alleviates the memory bottleneck by blending the pattern memory with the pattern learning and recognition logic.

The main innovation was finding a way to solve the "winner takes all problem" and allows a constant learning/recognition time, regardless of the number of processing elements (e.g. neurons) connected in parallel.

The first ZISC35 with 36 neurons was released in 1993 and the ZISC78 in 2000, both by IBM, which discontinued their manufacturing in 2001.

In August 2007, the CM1K (CogniMem 1,024 neurons) was introduced by CogniMem Ltd. CM1K was designed by Anne Menendez and Guy Paillet.

Practical uses of ZISC/CogniMem technology focus on pattern recognition, information retrieval (data mining), security and similar tasks.

References

↑ "CogniMem Technologies Inc. Technology Background". Retrieved 2012-03-08.

ZISC genesis and succession

External links

US Patent for ZISC hardware, issued to IBM/G.Paillet on April 15, 1997
Image Processing Using RBF like Neural Networks: A ZISC-036 Based Fully Parallel Implementation Solving Real World and Real Complexity Industrial Problems by K. Madani, G. de Trémiolles, and P. Tannhof
From CISC to RISC to ZISC by S. Liebman on lsmarketing.com
Neural Networks on Silicon at aboutAI.net
Zero instruction set computer at DMOZ
NeuroMem CM1K chip, successor of the ZISC, designed by G.Paillet/General Vision
CogniMem Technologies Inc. Massively Parallel Hardware Acceleration for Pattern Recognition

CPU technologies

Architecture	Von Neumann Harvard (Modified) Dataflow TTA

Instruction set	ASIP CISC RISC EDGE (TRIPS) VLIW (EPIC) MISC OISC NISC ZISC Comparison

Word size	1-bit 4-bit 8-bit 9-bit 10-bit 12-bit 15-bit 16-bit 18-bit 22-bit 24-bit 25-bit 26-bit 27-bit 31-bit 32-bit 33-bit 34-bit 36-bit 39-bit 40-bit 48-bit 50-bit 60-bit 64-bit 128-bit 256-bit 512-bit Variable

Execution	Instruction pipelining Bubble Operand forwarding Out-of-order execution Register renaming Speculative execution Branch predictor Memory dependence prediction Hazards

Parallel level	Bit Bit-serial Word Instruction Scalar Superscalar Task Thread Process Data Vector Memory

Multithreading	Temporal Simultaneous Preemptive Cooperative

Flynn's taxonomy	SISD SIMD MISD MIMD SPMD Addressing mode

Core count	Single-core processor Multi-core processor Manycore processor

Types	Digital signal processor (DSP) GPGPU Microcontroller Physics processing unit System on a chip (SoC) Cellular

Components	Address generation unit (AGU) Arithmetic logic unit (ALU) Barrel shifter Floating-point unit (FPU) Back-side bus Multiplexer Demultiplexer Registers Memory management unit (MMU) Translation lookaside buffer (TLB) Cache Register file Microcode Control unit Clock rate

Power management	APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating

Hardware security	Non-executable memory (NX bit) Bounds checking (Intel MPX) Hardware restriction (firmware) Software Guard Extensions (Intel SGX) Trusted Execution Technology Secure cryptoprocessor Hardware security module Hengzhi chip

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Zero instruction set computer

History

Design features

References

See also

External links