Xputer

The Xputer is a design for a reconfigurable computer, proposed by computer scientist Reiner Hartenstein in more than 300 peer-reviewed publications. Hartenstein uses various terms to describe the various innovations in the design, including config-ware, flow-ware, morph-ware, and "anti-machine".

The Xputer represents a move away from the traditional Von Neumann computer architecture, to a coarse-grained "soft Arithmetic logic unit (ALU)" architecture.[1] Parallelism is achieved by configurable elements known as reconfigurable datapath arrays (rDPA), organized in a two-dimensional array of ALU's similar to the KressArray.[1][2][3]

Architecture

The Xputer architecture is data-stream-based, and is the counterpart of the instruction-based von Neumann computer architecture.

The Xputer architecture was one of the first coarse-grained reconfigurable architectures,[2] and consists of a reconfigurable datapath array (rDPA) organized as a two-dimensional array of ALUs (rDPU).[2] The bus-width between ALU's were 32-bit in the first version of the Xputer.[2]

The ALUs (also known as rDPUs) are used for computing a single mathematical operation, such as addition, subtraction or multiplication, and can also be used purely for routing.[2]

ALUs are mesh-connected via three types of connections, and data-flow along these connections are managed by an address generation unit.[2]

Programs for the Xputer are written in the C language, and compiled for usage on the Xputer using the CoDeX compiler written by the author.[2] The CoDeX compiler maps suitable portions of the C program onto the Xputer's rDPA fabric.[2] The remainder of the program is executed on the host system, such as a personal computer.

rDPA

A reconfigurable datapath array (rDPA) is a semiconductor device containing reconfigurable data path units and programmable interconnects, first proposed by Rainer Kress in 1993, at the University of Kaiserslautern.

Instead of FPGAs (field-programmable gate arrays) having single bit configurable logic blocks (CLBs), rDPAs have multiple bits wide (for instance, 32 bit path width) reconfigurable datapath units (rDPUs).

Each rDPU can be configured to perform an individual function. These rDPUs and interconnects can be programmed after the manufacturing process by the customer/designer (hence the term "reconfigurable") so that the rDPA can perform whatever complex computation is needed. Because rDPUs are multiple bits wide (for instance, 32 bits), we talk about coarse-grained reconfigurability - in contrast to FPGAs with single-bit wide configurable logic blocks, called fine-gained reconfigurable.

rDPAs are structurally programmed from "config-ware" source code, compiled into pipe-networks to be mapped onto the rDPA. rDPAs are not instruction-stream-driven and have no instruction fetch at run time. rDPUs do not have a program counter.[4]

References

  1. 1 2 Field-Programmable Logic: Architectures, Synthesis and Applications, Reiner W. Hartenstein, Springer Science & Business Media, 24-Aug-1994
  2. 1 2 3 4 5 6 7 8 Compilation Techniques for Reconfigurable Architectures, Springer Science & Business Media, 02-Apr-2011
  3. ↑ Designing Embedded Processors: A Low Power Perspective, Springer Science & Business Media, 27-Jul-2007
  4. ↑ Reconfigurable System Design and Verification, CRC Press, 17-Feb-2009
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